1. Technical Field
The present invention relates to semiconductor memory devices such as DRAMs (dynamic random access memory) and, more particularly, to a system and method for performing a PASR (partial array self-refresh) operation, wherein a self-refresh operation for recharging stored data is performed on a portion of one or more selected memory banks comprising a cell array in a semiconductor memory device.
2. Description of Related Art
Semiconductor memory devices are largely classified as dynamic random access memories (DRAM) and static random access memories (SRAM). In an SRAM, a unit cell is implemented by four transistors constituting a latching mechanism. Unless the power is interrupted, the stored data is not volatile. Thus, a refresh operation is not necessary. However, in a DRAM, a unit cell is implemented by one transistor and one capacitor, and data is stored in the capacitor. A capacitor formed on a semiconductor substrate is not necessarily completely isolated from peripheral circuits, and therefore, it is possible for the data stored in the memory cell to be altered due to current leakage. Thus, a refresh operation for periodically recharging the data stored in the memory cell is required. A self-refresh operation of a semiconductor memory device is performed while sequentially varying internal addresses by an externally applied command signal.
According to recent trends in highly integrated, large capacitance semiconductor memory devices, a plurality of memory banks are commonly incorporated within a memory chip. Each memory bank is capable of outputting a predetermined amount of data. DRAMs installed on recent systems, including cordless telephones, data banks, Pentium(copyright)-type computer combined personal data assistance (PDA) systems, utilize most memory banks during a data communication mode, while utilizing only specific memory banks for storing data necessary for the system during a standby mode. In order to implement PDA systems, which commonly operate on battery power, it is necessary to minimize power consumption.
FIG. 1 is a block diagram of circuits utilized during a self-refresh operation for a conventional DRAM. In this specification, for the sake of convenience in explanation, a DRAM having four memory banks 101xe2x80x94i (i is an integer from 1 to 4) is illustrated. In FIG. 1, circuit portions related to a self-refresh operation are schematically shown while circuit portions unrelated to the self-refresh operation are not shown.
The respective memory banks 101xe2x80x94i have a plurality of memory cells arranged in columns and rows. Row decoders 103xe2x80x94i define row addresses in the corresponding memory bank. Column decoders 105_1 and 105_2 define column addresses in the corresponding memory bank. A refresh entry detector 107 detects a signal to enter self-refresh operation, and, in response, generates a refresh instruction signal PRFH. In response to a refresh instruction signal PRFH, an internal address generator and counter 109 spontaneously generates sequential addresses FRA1 to FRAn for a self-refresh operation, with the internal addresses being sequentially varied. A switch 111 receives external addresses A1 to An during a normal operating mode and receives the counting addresses FRA1 to FRAn during a refresh mode, and transfers the same to the row decoders 103xe2x80x94i as internal addresses RA1 to RAn.
The self-refresh operation is executed in the following manner. A semiconductor memory device enters into a self-refresh mode in response to an externally input command signal. Then, row addresses are sequentially increased or decreased at predetermined intervals. Word lines of a memory cell are selected sequentially by varying the row addresses. The charge accumulated in the capacitor corresponding to the selected word line is amplified by a sense amplifier and then stored in the capacitor again. Through such a refresh operation, the stored data is retained without loss. This self-refresh operation consumes a large amount of current during the process of sense-amplifying the data stored in the capacitor.
In the conventional DRAM shown in FIG. 1, a self-refresh operation is performed with respect to all memory banks. In other words, even if data is stored in only a specific memory bank, the self-refresh operation is performed on all memory banks.
Furthermore, although separate internal voltage generators 113xe2x80x94i (i is an integer from 1 to 4), including, for example, a back-bias voltage generator or an internal power-supply voltage generator, generally exist for each memory bank, they are all operated during a refresh operation.
As described above, the conventional DRAM performs a self-refresh operation with respect to all memory banks, resulting in unnecessary current dissipation. Also, if a self-refresh mode is entered, all the internal voltage generators existing for each memory bank operate, thereby further increasing current dissipation.
To address the above limitations, it is an object of the present invention to provide a semiconductor memory device, such as a dynamic random access memory (DRAM), having a plurality of memory banks, wherein the semiconductor memory device is capable of selectively performing a self-refresh operation with respect to individual memory banks and with respect to a portion of one or more selected memory banks.
The present invention provides various mechanisms for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion of one or more selected memory banks comprising a cell array in a semiconductor memory device. More specifically, the present invention provides mechanisms for performing a PASR operation for, e.g., xc2xd xc2xc, xe2x85x9, or {fraction (1/16)} of a selected memory bank.
In one aspect of the present invention, a PASR operation is performed by (1) controlling the generation of row addresses by a row address counter during a self-refresh operation and (2) controlling a self-refresh cycle generating circuit to adjust the self-refresh cycle output therefrom. The self-refresh cycle is adjusted in a manner that provides a reduction in the current dissipation during the PASR operation.
In another aspect of the present invention, a PASR operation is performed by controlling one or more row addresses corresponding to a partial cell array during a self-refresh operation, whereby a reduction in a self-refresh current dissipation is achieved by blocking the activation of a non-used block of a memory bank.
In yet another aspect of the present invention, a memory device comprises:
a plurality of memory banks each comprising a plurality of memory blocks; and
a self-refresh controlling circuit for selecting one of the memory banks and performing a self-refresh operation on one of the memory blocks of the selected memory bank.
In another aspect, a circuit for performing a PASR operation in a semiconductor memory device comprises:
a first pulse generator for generating a self-refresh cycle signal during a refresh operation of a semiconductor memory device, wherein the self-refresh cycle signal comprises a predetermined period T; and
a counter comprising a plurality of cycle counters for generating row address data in response to the self-refresh cycle signal, wherein the row address data is decoded to activate wordlines of a memory bank during the refresh operation of the semiconductor memory device,
wherein during a PASR operation, the counter is responsive to PASR control signal to disable operation of a cycle counter to mask an address bit output from the counter and wherein the first pulse generator is responsive to the PASR control signal to increase the predetermined period T of the self-refresh cycle signal.
In yet another aspect, a circuit for performing a PASR operation in a semiconductor memory device comprises:
a first pulse generator for generating a self-refresh cycle signal during a refresh operation of a semiconductor memory device;
a counter comprising a plurality of cycle counters for generating row address data in response to the self-refresh cycle signal, wherein the row address data is decoded to activate wordlines of a memory bank during the refresh operation of the semiconductor memory device;
a row address buffer for receiving the row address data output from the counter and outputting row addresses;
a row predecoder for decoding the row addresses output from the row address buffer to generate self-refresh address signals that are processed to activate wordlines of a memory bank during the refresh operation of the semiconductor memory device,
wherein during a PASR operation, the row address buffer is responsive to a PASR control signal to mask one or more address bits of the row address data to block activation of wordlines corresponding to a non-used portion of a memory bank.
In another aspect of the present invention, a circuit for performing a PASR operation in a semiconductor memory device comprises:
a first pulse generator for generating a self-refresh cycle signal during a refresh operation of a semiconductor memory device;
a counter comprising a plurality of cycle counters for generating row address data in response to the self-refresh cycle signal, wherein the row address data is decoded to activate wordlines of a memory bank during the refresh operation of the semiconductor memory device;
a row address buffer for receiving the row address data output from the counter and outputting row addresses;
a row predecoder for decoding the row addresses output from the row address buffer to generate self-refresh address signals that are processed to activate wordlines of a memory bank during the refresh operation of the semiconductor memory device,
wherein during a PASR operation, the row predecoder is responsive to a PASR control signal to mask one or more address bits of the row address data to block activation of wordlines corresponding to a non-used portion of a memory bank.